This invention relates generally to digital registers and, in particular, to a current mode multiple-generating register for generating one of several possible multiples of a binary number which is input thereto.
In the digital computer art it is often necessary to generate one of several possible multiples of a given binary number for a particular purpose. The present invention has utility, for example, in a high speed binary multiplier circuit which performs multiplication by means of an algorithm requiring the formation of partial products of the given multiplicand as a function of the given multiplier. The partial products are formed by generating multiples of .+-.1, .+-.2, or a 0 times the given multiplicand, depending upon the given multiplier, and summing those multiples into the partial products. The present invention also has utility in divider and data-shaping circuits and in other digital circuits employed in the processing of data in binary form, as will be apparent to one skilled in the art.
Related Invention Nos. 9 and 10 referenced above disclose multiple-generating registers. The present invention is directed to an improved multiple-generating register wherein such register may be operated at higher speeds and may be reconfigured for testing and diagnostic purposes.